Referring to FIG. 1, a conventional current mirror type sense amplifier circuit of semiconductor memory devices is illustrated. The sense amplifier is comprised of a reference voltage generating circuit 100 for generating a reference voltage, a sensing voltage generating circuit 200 for generating a sensing voltage, and a differential amplifier 300 for amplifying a difference voltage between the reference voltage and the sensing voltage.
A variable current sinker 270 has a current driving capability corresponding to the data state of a memory cell (not shown). That is, the variable current sinker 270 has current driving capability larger than that of a constant current sinker 170 when a memory cell stores a logic "0" (or logic "1") data, but it has current driving capability smaller than that of the constant current sinker 170 when the memory cell stores a logic "1" (or logic "0") data.
A sense amp enable signal SA is externally applied to an input of a complementary metal oxide semiconductor (CMOS) inverter formed by a P-channel MOS (PMOS) transistor 101 and an N-channel MOS (NMOS) transistor 102 within the reference voltage generating circuit 100. This signal SA is also applied to an input of an inverter formed by a PMOS transistor 201 and an NMOS transistor 202 in the sensing voltage generating circuit 200. NMOS precharge transistors 103 and 203 are provided for the voltage generating circuits 100 and 200. These precharge transistors 103 and 203 has their gates externally applied with a precharge control signal .phi.PRE. Current mirror type PMOS transistors 104 and 204 are provided for the reference voltage generating circuit 100 and the sensing voltage generating circuit 200, respectively. Between node N2 and the dummy data line DDL, placed is an NMOS transistor 105 whose gate is coupled to an output (i.e., node N1) of the inverter formed by transistors 101 and 102. Also, an NMOS transistor 205 is placed between the node N5 and the main data line DL. Gate of the transistor 205 is coupled to an output (i.e., node N4) of the inverter formed by the transistors 201 and 202. NMOS transistors 106 and 206 are further provided for the voltage generating circuit 100 and 200, respectively.
The sense amplifier is enabled when the sense amp enable signal SA changes from a logic high level to a logic low level. With the application of the low level signal SA, PMOS transistors 101 and 201 are turned on, thus the voltage levels of the nodes N1 and N4 go high so as to make NMOS transistors 105 and 205 conductive. Thereafter, when the signal .phi.PRE goes high, the transistors 103 and 203 are turned on so that the voltage levels of nodes N2, N3, N5 and N6 (i.e., data lines DDL and DL) start to increase. The increase of the voltage levels of the nodes N3 and N6 are stopped at a point that respective current driving capacities of the PMOS transistors 101 and 201 balance with those of the NMOS transistors 106 and 206.
After a given precharge period, the precharge control signal .phi.PRE becomes inactive low again and so the transistors 103 and 203 are rendered off At this time, the transistors 104 and 204 deliver the same amount of current as sinks to the ground voltage Vss via the current sinker 170 so as to maintain the voltage level of node N2 constant. This constant voltage is applied to the input IN1 of the differential amplifier 300 as a reference voltage. Owing to the current mirror arrangement, the transistors 204 conducts the same current as the transistor 104 does. So, if the variable current sinker 270 has a current driving capability larger than that of the constant current sinker 170, the sensing voltage level on node N5 becomes lower than the reference voltage level on the node N1. On the contrary, if the variable current sinker 270 has a current driving capability smaller than that of the constant current sinker 170, the sensing voltage of node N5 becomes higher than the reference voltage on the node N2. These voltage differences are amplified by the differential amplifier 300.
In general, the amount of current flowing through a MOS transistor is proportional to the gate-source voltage. NMOS transistors 103 and 203 have their sources coupled to the nodes N2 and N5 of different voltages, respectively, even though their drains and gates are applied with a constant voltage (i.e., power supply voltage) during a precharge period. Thus, the transistor 203 does not have the same current driving ability as the transistor 103 during the precharge period. Due to these differences in current, the voltage difference between the nodes N2 and N5 is not caused only by the difference between the current driving abilities of the current sinkers 170 and 270. That is, when the variable current sinker 270 has current driving capability larger than that of the constant current sinker 170 during the precharge period, the node N5 is expected to be pulled down faster than the node N2, but not because the node N5 is lower than the node N2 and so the transistor 203 conducts current larger than that of the transistor 103; In addition, when the variable current sinker 270 has current driving capability smaller than that of the constant current sinker 170 during the precharge period, the node N5 is expected to be pulled up faster than the node N2, but not because the node N5 is higher than the node N2 and so the transistor 203 conducts current smaller than that of the transistor 103.
As described above, in case the transistors 103 and 203 cannot deliver the same current to the nodes N2 and N5 during a precharge period, (1) there may be a very small difference in the voltage levels of the nodes N2 and N5, thereby reducing the data sensing speed and the sensing margin, (2) in the worst cases, the voltage levels of the nodes N2 and N5 may be reversed so that reading errors will occur.
To overcome such shortcomings, the use of the NMOS precharge transistors 103 and 203 should be restricted only to the early stage of precharging the data lines DDL and DL rapidly, and only the PMOS precharge transistors 104 and 204 having the same current driving capability must be devoted to the remaining stage of the precharge period that requires the precise precharge control.
In the above-described conventional sense amplifier circuit, the NMOS precharge transistors 103 and 203 are shut off compulsorily and abruptly by the external precharge control signal .phi.PRE. It is however not easy to control the inactivation timing of the precharge control signal .phi.PRE, and it is also desirable that the precharge transistors 103 and 203 are gradually shut off since such an abrupt shut-off will cause an unexpected transient in data sensing.
Moreover, as the precharge voltage levels on the nodes N2 and N5 increase during a precharge period, the source voltage levels of NMOS transistors 103 and 203 also increase and so their gate-source voltage decrease. Thus, NMOS transistors 103 and 203, as well as PMOS transistors 104 and 204, have their higher threshold voltages than expected due to the body effect (these threshold voltage variations due to the body effect can also be affected by the various process variations). As a result of this, the transistors 103 and 203 will shut off naturally before the discharge control signal .phi.PRE becomes inactive. Such a natural shut-off also appears in the PMOS transistors 104 and 204 having the same current driving ability owing to their current mirror arrangement so that the transistors 104 and 204 will shut off in worst case before the shut-off of NMOS transistors 103 and 203 that usually have different current driving abilities, thereby causing poor sensing performance and reading errors.